The main objective of the DRAGON project was to research and use new design methodologies and architectural innovations, based on reconfigurability and state-of-the-art digital CMOS technology, in order to break the barriers imposed by the lack of scaling properties of analog components. With this concept, distinct reductions in cost, size and energy consumption for multi-standard cellular handsets would be achieved, while higher demands on data rate could be met. Data rates have been increasing steadily, therefore the energy consumption per transmitted or received data needs to be reduced in order to save energy and avoid thermal problems. Wireless data services are becoming an attractive low-cost alternative to be used in novel applications.
In the DRAGON project a design platform comprising multi-standard transceiver specifications and novel flexible architecture was developed. The number of required external components, such as analog filters, was replaced by reconfigurable digital CMOS (Complementary Metal Oxide Semiconductor) circuitry; and critical building-blocs were implemented to demonstrate proof-of-concept, both of the architecture and design methodology. All critical building-blocks were fabricated, tested, and demonstrated in state-of-the-art CMOS technology. The project results were also provided to standardisation bodies, thus allowing an alignment of requirements to technology limits.
The strategy was aimed at concurrently resolving a number of critical path issues, which acted as impediments to the design and creation of future platforms. “Design Methods for Radio Architectures” were used as a lead example and work horse for the European design methodology “GOing Nanoscale”.
The issues were embodied in the design of the five technical and one management work packages. Each work package was addressed by a team of specialists with advanced domain knowledge, which was brought to bear on each of the technical core issues.
The development of DRAGON was partitioned in the following work packages:
- WP01 - "Requirements and standardisation" was responsible for the task of developing and maintaining a link-budget tool for the transceiver system. This targeted highly innovative architectures and new ways of partitioning the typical block requirements, e.g. selectivity, linearity, noise or gain. The work package also monitored state-of-the-art technology and the standardisation work carried out in the 3GPP RAN4 group and fed this information to the WPs.
- WP02 - "Low power concept and architecture" developed an efficient architecture and a concept fullfilling the specification for the LTE transceiver defined in WP01 activities.
- WP03 - "Innovative Miniturised Receiver Design" had the goal of developing a design plattform that first intended to merge the on-chip channelselect filter with the receive ADC to eliminate much of the circuit complexity.
- WP04 - "Smart transmitters and power amplifiers" was concerned with the design of the transmitter part of a transceiver. Also the design of the antenna-SMPA interface and the design of the digital modulators were taken into account during this WP.
- WP05 - "Proof of concept and verification" provided the logistic platform to access state-of-the-art nanometer CMOS design technology. Further the specification, which was defined in WP01, had to be compared to the measurement results.
- WP06 - "Project Management and dissemination" aimed at an effective operational management with regard to contractual, financial, legal, technical, administrative and ethical management issues and focused on a coordinated management of dissemination and exploitation for the DRAGON project.
The performance offered by wireless standards has improved steadily over the last decades. There are two main reasons:
- Society today increasingly asks for wireless systems since they have the potential to enhance comfort and pleasure. More importantly even, wireless technologies can help to support independent living and save costs in health care for an ageing society.
- Industrial progress relies on continued growth of wireless capacity. Not only more and more people count on mobile broadband services in their professional activities, also the number of objects connected by wireless interfaces is dramatically increasing.
Objective 1 – Miniaturisation of Complex Radio Systems
Terminals need radios that support multiple standards and data rates up to 1 Gbit/s. In order to avoid a serious impact on cost, size and weight of the terminal due to increasing numbers of radios and their capacity, miniaturization through design of innovative reconfigurable architectures in nanoscale technologies is crucial. Terminals need radios that support multiple standards and data rates up to 1 Gbit/s.
Objective 2 – Design Methodologies for Energy Efficient Solutions for High Performance Systems
The new, innovative designs should be capable of reaching the same level of average power consumption as dedicated solutions. DRAGON aimed at obtaining a 50% energy reduction compared to classical systems.
Objective 3 – Multi-Functional / Multi-Purpose Devices
The proposed multi-functional designs in DRAGON have allowed paying off non-recurring engineering costs (NRE) in chip design by re-using the same system in a broad range of applications. Further, DRAGON aimed at supporting more than two standards in one building block which was, at the time, the maximum number that could be achieved.
Objective 4 – Proof of Concept by Silicon Demonstrators
The design of innovative architectures in the most advanced commercial CMOS technologies was not only used to illustrate and prove the DRAGON project results, but, more importantly, will give European companies the confidence that the disruptive design paths are ready for adoption, and convince them of their significant added value.
Miniaturized low-cost receiver
- significant area and power reduction by cleverly exploiting digital CMOS process technology speed;
- density advances for implementation of blocks with analog and RF functionality;
- 40% reduction in power consumption;
- 20% reduction in chip area compared to a corresponding conventional solution;
- in the baseband ADC, resolution increased by 9dB at negligible area cost by estimating residue voltage using digital comparators.
High efficiency multi-mode transmitter
- significant improvement in power-added efficiency for integrated CMOS-based transmitter;
- almost 26dBm of peak output power while also capable of delivering 22.5dBm LTE-compliant average output power at 18.9% PAE;
- over 2.5 times better than a similar class-B PA